3. Hardware description language. Hardware Description Language (HDL) is a computer language used to design hardware electronic systems. It uses software programming to describe the logical functions, circuit structures and connection forms of electronic systems. Compared with traditional gate-level description methods, it More suitable for the design of large-scale systems. For example, a 32-bit adder requires 500 to 1000 gates to be input using the graphics input software, and only one line of "A=B+C" can be written using the VHDL language. And the VHDL language is readable, easy to modify and find errors. Early hardware description languages, such as ABEL, HDL, and AHDL, were developed by different EDA vendors, were incompatible with each other, and did not support multi-level design. Inter-level translation work was done manually. In order to overcome the above deficiencies, in 1985 the US Department of Defense officially launched the high-speed integrated circuit hardware description language VHDL. In 1987, the IEEE adopted VHDL as the hardware description language standard (IEEE STD-1076).
VHDL is a comprehensive hardware description language that includes system behavioral levels. Multiple transfer levels of register transfer level and logic gate level support mixed descriptions of structure, data flow and behavior. Therefore, VHDL covers almost all functions of hardware Russian language, and the whole top-down or bottom-up The circuit design process can be done with VHDL. VHDL also has the following advantages: (1) VHDL's wide-range description capability makes it the core of high-level design, which increases the designer's focus to the realization and debugging of system functions, and spends less effort on physical implementation. (2) VHDL can be used for complex control logic design with simple and clear code description, flexible and convenient, and also facilitates the exchange, preservation and reuse of design results. (3) The design of VHDL does not depend on a specific device, which facilitates the conversion of the process. (4) VHDL is a standard language supported by many EDA vendors, so portability is good.
4. EDA System Pivot Structure The EDA System Framework (FRAMEWORK) is a set of specifications for configuring and using EDA software packages. At present, the main EDA systems have established framework structures, such as CADENCE's Design Framework and Mentor's Falcon Framework, and these frameworks are in compliance with the unified technical standards set by the international CFI organization. The framework structure optimizes the combination of tool software from different EDA vendors, integrates them in a single, easy-to-manage environment, and supports the transfer and sharing of information between tasks, designers, and throughout product development. It is the basis for the implementation of concurrent engineering and top-down design.
Every advancement in EDA technology has caused a leap in the design hierarchy, from the design level, the physical design (CAD) in the 1970s, the circuit-level design (CAE) in the 1980s, and the system-level design in the 1990s. (EDA). The physical level design mainly refers to the IC layout design, which is generally completed by semiconductor manufacturers and does not have much significance for electronic engineers. Therefore, this paper focuses on circuit level design and system level design.
1. The circuit level design circuit level design workflow is shown in Figure 2. After the electronic engineer accepts the system design task, first determine the design plan, and select the appropriate components that can realize the solution, and then design the circuit schematic according to the specific components. Then the first simulation is carried out, including logic simulation of digital circuit, fault analysis, AC/DC analysis of analog circuit, and transient analysis. In the system simulation, the component model library must be supported. The simulated human output waveform on the computer replaces the signal source and oscilloscope in the actual circuit debugging. This simulation is mainly to verify the correctness of the design in terms of function.
After the simulation is passed, the automatic layout of the PCB board is performed according to the electrical connection network table generated by the schematic diagram. Post-PCB analysis, including thermal analysis, noise and disturbance analysis, electromagnetic compatibility analysis, reliability analysis, etc., can be performed before the PCB board is fabricated, and the analyzed result parameters can be back-referenced to the circuit diagram for the second simulation. Also known as post-simulation. The post-simulation is mainly to verify the feasibility of the PCB in the actual working environment.
It can be seen that the circuit-level EDA technology enables electronic engineers to fully understand the functional and physical characteristics of the system before the actual electronic system is generated, thereby eliminating development risks in the design phase, shortening development time and reducing development. cost.
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